The EDS Mini-colloquium is organized by the IEEE EDS Spain Chapter.Tuesday 8
Memristors have attracted enormous interest due to their excellent capability to store digital information, and they are being considered to be a key element to build future artificial neural networks for bio-inspired neuromorphic computing systems. Recent works have shown that memristors made of layered two-dimensional (2D) materials can exhibit performances that traditional memristors (made of transition metal oxides) do not show, such as excellent transparency and flexibility, high-temperature stability, and unique controllability of the conductance potentiation, depression and relaxation. However, most studies on 2D materials based memristors focused on single devices, and system level performances like yield and device-to-device variability have never been analyzed in depth, despite the great interest that they have raised. In this talk, I will present the first wafer-scale statistical analysis of high-density memristive crossbar arrays made of 2D layered materials, their nanoscale electronic characterization with conductive atomic force microscopy, and their application to neuromorphic computing.
Scaling has been the main driver for CMOS technology, leading to enhanced device performance, i.e., speed and integration density. From an analog/RF applications perspective, an important parameter is the low-frequency (LF) noise and one may wonder how scaling affects the power spectral density (PSD). As the PSD of most relevant noise mechanisms (1/f noise, Generation-Recombination (GR) noise, Random Telegraph Noise – RTN) scales with the inverse area, one can expect an increase in noise for smaller technology nodes.
In this lecture, a general introduction to the LF noise in MOS transistors will be provided and the impact of scaling the feature size will be discussed. At the same time, it will be shown that the device architecture, e.g., planar, versus FinFET, versus nanowire or nanosheet (NW; NS) has a strong impact on the average normalized noise PSD. In conclusion, it can be stated that moving toward nanowire and nanosheet (or forksheet) architectures yields a marked reduction in the average area-normalized 1/f noise beyond the expected geometrical scaling with Equivalent Oxide Thickness. This holds great promise for future analog/RF applications of sub-7 nm CMOS nodes.
Polymer solar cells are considered as a promising renewable energy source because of their light-weight, high transparency, possibility of fabrication in large areas and inexpensive solar energy production. These solar cells are based in the junction of two different organic semiconducting materials, one donor and one acceptor. The most efficient devices to date are the bulk heterojunction cells, obtained from a mixture of the donor and acceptor materials, which provides an enormous interfacial surface.
In the last years, advances in polymer-based organic solar cells have been possible due to different approaches such as design of new structures and synthesis of new materials such as small molecule and polymers with low band-gaps, control of the nanoscale morphology, new interfacial transport layers, variation of the ratio of the donor/acceptor in the bulk heterojunction, application of thermal or solvent annealing process, among others. As a result, recently, power conversion efficiencies over 18% are obtained. However, there are still some problems to solve such as the stability, more efficient architectures and degradation process of the polymeric solar cells. In this lecture, we will present the perspectives and recent advances made in polymer solar cells, design and synthesis of new polymers and in particular the active layer morphology, interfacial layers and stability. We will also discuss the basic device operation and various parameters limiting their efficiency and their possible improvements.
In this talk I will briefly review the evolution of the memdiode (diode + memory) model for resistive RAMs (RRAM) and its most recent applications to the field of neuromorphic computing. RRAMs are based on the resistive switching mechanism, which consists in the reversible and nonvolatile change of resistance state of a thin oxide layer caused by an external electrical stimulus. The memdiode model is based on an extension of Prof. Chua’s memristor theory, the so-called fourth electrical element. I will show how the memdiode equations can be easily transformed into a behavioral equivalent electric circuit suitable for the compact modeling of RRAMs in SPICE.
We review the physics and modeling of Organic Thin-Film Transistors (OTFTs) and Amorphous Oxide Semiconductors Thin-Film Transistors ( AOS TFTs). We analyze the electrostatic and charge transport mechanisms in these devices. We demonstrate that compact OTFTs and AOS TFTs models can be developed by using analytical approximate solutions of Poisson's equation considering exponential Density of States (DOS) and on a transport model based on the combination of carrier hopping between localized states with drift current of free carriers. The resulting field-effect mobility expressions are power laws of the gate voltage overdrive. Analytical expressions are developed from the deep subthreshold regime to the well above threshold one. Besides, we present direct methods to extract model parameters. We show that most key parameters are extracted applying an integral operator to the measured transfer characteristics. We analyze drain current characteristics from 150K to 350K and show the temperature dependences of the extracted parameters. We also present capacitance modeling frameworks for OTFTs and AOS TFTs which are consistent with the developed drain current models. The modeled C-V characteristics are successfully validated by comparison with experimental data and TCAD simulations at different temperatures.
Silicon electronics have revolutionized the processing and handling of information. The high temperatures required to create crystalline silicon devices, however, has limited the application of crystalline silicon to sensing systems that work in a small and mechanically rigid form factor. The development of inorganic and organic thin film electronics has launched a second revolution in electronics, granting the ability to process electronically active materials at low temperatures. This has allowed for two exciting opportunities: the ability to build electronic devices on the same size scale as the systems they interact with, and the ability to integrate electronic materials on a range of substrates including the back-end of CMOS integrated circuits, electronically active substrates, and flexible materials.
Our group has been working on the hybrid integration of organic semiconductors, thin film piezoelectrics, and laser-recrystallized silicon with active substrates to implement a range of new functionalities. In this presentation, I'll show how thin film electronics and the hybrid integration enabled by new semiconductor systems and process options allows for active and spatially localized control of systems that are typically used in a single element format. Devices we have developed include single chip PCR systems, miniature spectrometers, devices for blood flow analysis, large area and miniature microphones, integrated on-chip filters, and active matrix micro-LED displays. These approaches unlock new applications in healthcare, sensing, displays, and communications.
As predicted by Gordon Moore more than 50 years ago, the number of transistors able to fit on a computer chip has doubled approximately every 18 months. But if the trend is to continue for the years to come, it will have to be with technology other than the conventional CMOS design. As the size of transistors gets down to the nanoscale, CMOS devices begin to suffer from several issues, in particular, increased resistance, decreased channel mobility, and increased manufacturing costs. To overcome the challenges involved with scaling, researchers from around the world have begun to look for alternatives to CMOS technology. Our recently introduced concept, called nano-electron-fluidic logic (NFL), is based, not on electron particle transport, but on the generation, propagation, and manipulation of surface plasma waves (plasmons) in an electron fluid. NFL gates are projected to exhibit femtojoule power dissipations and femtosecond switching speeds at finite temperatures, while taking full advantage of established semiconductor manufacturing infrastructure. NFL represents a paradigm shift in digital technology, and is poised as a strong candidate for “beyond-CMOS” digital logic. This talk presents the theory, physics and design principles of NFL.